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MAX1266ACEI Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1266ACEI Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 19 page 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 9 BIT PD1, PD0 0 D7, D6 PD1 and PD0 select the various clock and power-down modes. Full power-down mode. Clock mode is unaffected. D5 ACQMOD ACQMOD = 0: Internal acquisition mode ACQMOD = 1: External acquisition mode NAME FUNCTIONAL DESCRIPTION 0 1 0 Standby power-down mode. Clock mode is unaffected. 0 1 1 Normal operation mode. External clock mode selected. 1 Normal operation mode. Internal clock mode selected. D4 SGL/DIF SGL/DIF = 0: Pseudo-differential analog input mode SGL/DIF = 1: Single-ended analog input mode In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage difference between two channels is measured (Tables 2 and 4). D3 UNI/BIP UNI/BIP = 0: Bipolar mode UNI/BIP = 1: Unipolar mode In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. D2, D1, D0 A2, A1, A0 Address bits A2, A1, A0 select which of the 6/2 (MAX1266/MAX1268) channels is to be converted (Tables 2 and 3). Table 1. Control-Byte Functional Description Single-Ended and Pseudo-Differential Operation The sampling architecture of the ADC’s analog com- parator is illustrated in the equivalent input circuits of Figure 3. In single-ended mode, IN+ is internally switched to channels CH0–CH5 for the MAX1266 (Figure 3a) and to CH0–CH1 for the MAX1268 (Figure 3b), while IN- is switched to COM (Table 2). In differen- tial mode, IN+ and IN- are selected from analog input pairs (Table 3) and are internally switched to either of the analog inputs. This configuration is pseudo-differen- tial to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5 LSB (±0.1 LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected input) to GND. Figure 3a. MAX1266 Simplified Input Structure Figure 3b. MAX1268 Simplified Input Structure CH0 CH1 CH3 CH2 CH5 CH4 COM CSWITCH TRACK T/H SWITCH RIN 800 Ω CHOLD 12pF HOLD 12-BIT CAPACITIVE DAC VREF ZERO COMPARATOR – + SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS CH0/CH1, CH2/CH3, AND CH4/CH5 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. INPUT MUX CH0 CH1 COM CSWITCH TRACK T/H SWITCH RIN 800 Ω HOLD ZERO COMPARATOR – + SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR CH0/CH1 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. INPUT MUX CHOLD 12pF 12-BIT CAPACITIVE DAC VREF |
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