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BCRTM-11
NAME
TYPE
ACTIVE
DESCRIPTION
CLK
MCLK
MCLKD2
21
65
71
J5
C5
A3
TI
TI
TO
Memory Clock Divided by Two. This signal is the
Memory Clock input divided by two. It assists the
host subsystem in synchronizing DMA events.
Clock. The 12MHz input clock requires a 50%
± 10% duty cycle with an accuracy of± 0.01%. The accuracy
is required in order to meet the Manchester encoding/
decoding requirements of MIL-STD-1553.
Memory Clock. This is the input clock frequency the BCRTM
uses for memory accesses. The memory cycle time is equal
to two MCLK cycles. Therefore, RAM access time is
dependent upon the chosen MCLK frequency (6MHz
minimum, 12MHz maximum). Please see the BCRTM DMA
timing diagrams in this data sheet.
--
--
--
CLOCK SIGNALS
PIN NUMBER
LCC
PGA
NAME
TYPE
ACTIVE
DESCRIPTION
23
43
64
84
1
22
42
63
L6
F9
G13
C7
J3
N8
F10
B6
PWR
PWR
PWR
PWR
GND
GND
GND
GND
+5V
+5V
+5V
+5V
Ground
Ground
Ground
Ground
--
--
--
--
--
--
--
--
POWER AND
VDD
VSS
VDD
VDD
VDD
VSS
VSS
VSS
PIN NUMBER
LCC
PGA
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