8-453

HS-6564RH

Timing Waveforms

READ CYCLE

TRUTH TABLE

TIME

REFERENCE

INPUTS

OUTPUT

Q

FUNCTION

E

W

A

-1

H

X

X

Z

Memory Disabled

0

H

V

Z

Cycle Begins, Addresses are Latched

1

L

H

X

X

Output Enabled

2

L

H

X

V

Output Valid

3

H

X

V

Read Accomplished

4

H

X

X

Z

Prepare for Next Cycle (Same as -1)

5

H

V

Z

Cycle Ends, Next Cycle Begins (Same as 0)

TELEL

TAVEL

TELAX

NEXT ADD

TEHEL

TEHQZ

HIGH-Z

TELQX

TELQV

ADD VALID

TEHEL

HIGH

HIGH-Z

TELEH

-1

0

1

2

3

4

5

TAVEL

A

E

Q

W

TIME

REFERENCE

The address information is latched in the on chip registers

on the falling edge of E (T = 0). Minimum address set up and

hold time requirements must be met. After the required hold

time, the addresses may change state without affecting

device operation. During time (T = 1) the output becomes

enabled but data is not valid until during time (T = 2). W must

remain high until after time (T = 2). After the output data has

been read, E may return high (T = 3). This will disable the

output buffer and ready the RAM for the next memory cycle

(T = 4).