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HSP43220883 Datasheet(PDF) 3 Page - Intersil Corporation |
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HSP43220883 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 7 page 3 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed and 100% Tested PARAMETER SYMBOL (NOTES) (NOTE 5) GROUP A SUB- GROUPS TEMP (oC) -15 (15MHz) -25 (25.6MHz) UNITS MIN MAX MIN MAX Input Clock Period tCK 9, 10, 11 -55 ≤ TA ≤ 125 66 - 39 - ns FIR Clock Period tFIR 9, 10, 11 -55 ≤ TA ≤ 125 66 - 39 - ns Clock Pulse Width Low tSPWL 9, 10, 11 -55 ≤ TA ≤ 125 26 - 16 - ns Clock Pulse Width High tSPWH 9, 10, 11 -55 ≤ TA ≤ 125 26 - 16 - ns Clock Skew Between FIR_CLK and CK_IN tSK 9, 10, 11 -55 ≤ TA ≤ 125 0 TFIR -250TFIR -19 ns RESET Pulse Width Low tRSPW 9, 10, 11 -55 ≤ TA ≤ 125 4 TCK -4 TCK -ns Recovery Time On RESET tRTRS 9, 10, 11 -55 ≤ TA ≤ 125 8 TCK -8 TCK -ns ASTARTIN Pulse Width Low tAST 9, 10, 11 -55 ≤ TA ≤ 125 TCK +10 - TCK +10 - ns STARTOUT Delay From CK_IN tSTOD 9, 10, 11 -55 ≤ TA ≤ 125 - 35 - 20 ns STARTIN Setup to CK _IN tSTIC 9, 10, 11 -55 ≤ TA ≤ 125 25 - 15 - ns Setup Time on DATA_IN tSET 9, 10, 11 -55 ≤ TA ≤ 125 20 - 16 - ns Hold Time on All Inputs tHOLD 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Write Pulse Width Low tWL 9, 10, 11 -55 ≤ TA ≤ 125 26 - 15 - ns Write pulse Width High tWH 9, 10, 11 -55 ≤ TA ≤ 125 26 - 20 - ns Setup Time on Address Bus Before the Rising Edge of Write tSTADD 9, 10, 11 -55 ≤ TA ≤ 125 28 - 24 - ns Setup Time on Chip Select Before the Rising Edge of Write tSTCS 9, 10, 11 -55 ≤ TA ≤ 125 28 - 24 - ns Setup Time on Control Bus Before the Rising Edge of Write tSTCB 9, 10, 11 -55 ≤ TA ≤ 125 28 - 24 - ns DATA_RDY Pulse Width Low tDRPWL 9, 10, 11 -55 ≤ TA ≤ 125 2TFIR -20 - 2TFIR -10 - ns DATA_OUT Delay Relative to FIR_CK tFIRDV 9, 10, 11 -55 ≤ TA ≤ 125 - 50 - 35 ns DATA_RDY Valid Delay Relative to FIR_CK tFIRDR 9, 10, 11 -55 ≤ TA ≤ 125 - 35 - 25 ns DATA_OUT Delay Relative to OUT_SELH tOUT 9, 10, 11 -55 ≤ TA ≤ 125 - 30 - 25 ns Output Enable to Data Out Valid tOEV Note 6 9, 10, 11 -55 ≤ TA ≤ 125 - 20 - 20 ns NOTES: 5. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V. 6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF. HSP43220/883 |
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