3

TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS

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PARAMETER

SYMBOL

(NOTES)

(NOTE 5)

GROUP A

SUB-

GROUPS

-15 (15MHz)

-25 (25.6MHz)

UNITS

MIN

MAX

MIN

MAX

Input Clock Period

9, 10, 11

-55

66

-

39

-

ns

FIR Clock Period

9, 10, 11

-55

66

-

39

-

ns

Clock Pulse Width Low

9, 10, 11

-55

26

-

16

-

ns

Clock Pulse Width High

9, 10, 11

-55

26

-

16

-

ns

Clock Skew Between

FIR_CLK and CK_IN

9, 10, 11

-55

0

ns

RESET Pulse Width Low

9, 10, 11

-55

-ns

Recovery Time On

RESET

9, 10, 11

-55

-ns

ASTARTIN Pulse Width

Low

9, 10, 11

-55

-

-

ns

STARTOUT Delay From

CK_IN

9, 10, 11

-55

-

35

-

20

ns

STARTIN Setup to

CK _IN

9, 10, 11

-55

25

-

15

-

ns

Setup Time on DATA_IN

9, 10, 11

-55

20

-

16

-

ns

Hold Time on All Inputs

9, 10, 11

-55

0

-

0

-

ns

Write Pulse Width Low

9, 10, 11

-55

26

-

15

-

ns

Write pulse Width High

9, 10, 11

-55

26

-

20

-

ns

Setup Time on Address

Bus Before the Rising

Edge of Write

9, 10, 11

-55

28

-

24

-

ns

Setup Time on Chip

Select Before the

Rising Edge of Write

9, 10, 11

-55

28

-

24

-

ns

Setup Time on Control

Bus Before the Rising

Edge of Write

9, 10, 11

-55

28

-

24

-

ns

DATA_RDY Pulse Width

Low

9, 10, 11

-55

-

-

ns

DATA_OUT Delay

Relative to FIR_CK

9, 10, 11

-55

-

50

-

35

ns

DATA_RDY Valid Delay

Relative to FIR_CK

9, 10, 11

-55

-

35

-

25

ns

DATA_OUT Delay

Relative to OUT_SELH

9, 10, 11

-55

-

30

-

25

ns

Output Enable to

Data Out Valid

Note 6

9, 10, 11

-55

-

20

-

20

ns

NOTES:

made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V.

6. Transition is measured at

HSP43220/883