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ICL7112LCDL Datasheet(PDF) 8 Page - Intersil Corporation |
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ICL7112LCDL Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 14 page 6-8 By adding a three-state buffer and two control gates, the End-of-Conversion (EOC) output can be used to control a “Start and Poll” interface (Figure 6). In this mode, the A0 and CS lines connect the EOC output to the data bus along with the most significant byte of data. After pulsing the WR line to initiate a conversion, the microprocessor continually reads the most significant byte until it detects a high level on the EOC bit. The “Start and Poll” interface increases data throughput compared with the “Start and Wait” method by eliminating delays between the conversion termination and the microprocessor read operation. Other interface configurations can be used to increase data throughput without monopolizing the microprocessor during waiting or polling operations by using the EOC line as an interrupt generator as shown in Figure 7. After the conver- sion cycle is initiated, the microprocessor can continue to execute routines that are independent of the A/D converter until the converter’s output register actually holds valid data. For fastest data throughput, the ICL7112 can be connected directly to the data bus but controlled by way of a Direct VIN VREF AGND DGND ICL7112 VIN + SOURCE - VREF - SOURCE + FIGURE 4. RECOMMENDED GROUNDING TECHNIQUE TO ELIMINATE GROUND LOOP ERRORS ICL7112 A0 CS RD BUS OVR D8 - D11 D0 - D7 WR A0 - AN CS RD µP OVR D0 - D7 WR ADDRESS DECODE ADDRESS BUS DATA BUS A0 READ LOW BYTE READ HIGH BYTE START CONVERSION WAIT RD A0 CS WR FIGURE 5. “START AND WAIT” OPERATION ICL7112 |
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