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EP2AGX45DF25I5 Datasheet(PDF) 40 Page - Altera Corporation |
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EP2AGX45DF25I5 Datasheet(HTML) 40 Page - Altera Corporation |
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40 / 90 page  1–32 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation -3 dB Bandwidth PCIe Gen1 2.5 - 3.5 MHz PCIe Gen2 6 - 8 MHz (OIF) CEI PHY at 4.976 Gbps 7 - 11 MHz (OIF) CEI PHY at 6.375 Gbps 5 - 10 MHz XAUI 2 - 4 MHz SRIO 1.25 Gbps 3 - 5.5 MHz SRIO 2.5 Gbps 3 - 5.5 MHz SRIO 3.125 Gbps 2 - 4 MHz GIGE 2.5 - 4.5 MHz SONET OC12 1.5 - 2.5 MHz SONET OC48 3.5 - 6 MHz Transceiver-FPGA Fabric Interface Interface speed — 25 — 325 25 — 250 MHz Digital reset pulse width — Minimum is two parallel clock cycles — Notes to Table 1–35: (1) The 3x speed grade is the fastest speed grade offered in the following Arria II GZ devices: EP2AGZ225, EP2AGZ300, and EP2AGZ350. (2) The rise and fall time transition is specified from 20% to 80%. (3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f. (4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. (5) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. (6) The device cannot tolerate prolonged operation at this absolute maximum. (7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS. (8) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive the minimum eye opening requirement with Receiver Equalization enabled. (9) The rate matcher supports only up to ± 300 ppm. (10) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–1 on page 1–33. (11) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1–1 on page 1–33. (12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–1 on page 1–33. (13) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–2 on page 1–33. (14) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the Transceiver Clocking for Arria II Devices chapter. (15) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (16) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 5 of 5) Symbol/ Description Conditions –C3 and –I3 (1) –C4 and –I4 Unit Min Typ Max Min Typ Max |
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