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SC220C0PTAV Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc

Part # SC220C0PTAV
Description  XpressFlow 2020 Ethernet Routing Switch Chipset
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

SC220C0PTAV Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc

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PRELIMINARY
INFORMATION
© 1998 Vertex Networks, Inc.
1
Rev. 4.5 – February
1999
Distinctive Characteristics
t
Highly integrated central switch controller
t
State of the art 0.35 micron 3.3 Volt CMOS
process
t
256-PIN PQFP package
t
Operating frequency
◊ -40
40 MHz maximum
◊ -50
50 MHz maximum
◊ -66
66 MHz maximum
t
16-bit external CAM interface
◊ Supports ½k to 16k MAC addresses
t
32-bit Control Buffer Memory interface
◊ Supports 128k to 1M bytes
◊ Utilize high performance 32-bit Syn-
chronous Burst SRAM
t
Hardware assisted Buffer and Queue Man-
agement to minimize CPU overhead
t
32-bit Management Bus I/O interface
◊ Allows host to access CAM and Control
Buffer Memory
◊ Supports Big and Little Endian CPUs
◊ Direct interface with various different
standard microprocessors including
386, 486 families and Motorola MPC se-
ries embedded processors
t
32-bit XpressFlow Bus Interface
◊ Switching bandwidth
−1.28 Gbps @ 40 MHz system clock
−1.60 Gbps @ 50 MHz system clock
−2.10 Gbps @ 66.67 MHz system clock
◊ Supports up to 8 Multi-port Network Ac-
cess Controllers
◊ XpressFlow Bus access arbitration
◊ XpressFlow Bus data transfer load
regulation
t
Full IP Switching
◊ Addresses resolved by SC220
t
MAC Address Mapping Table
◊ Supports either CAM based or SRAM
based Switching data base
SC220 – XpressFlow Engine
XpressFlow 2020 Ethernet Routing Switch Chipset
CONTROL
BUFFER
MEMORY
XpressFlow BUS
XpressFlow BUS
32
32
32
SC220
XpressFlow
ENGINE
ADDRESS
MAPPING
TABLE
16
CAM
(Optional)
SC220 - XpressFlow Engine
General Description
The XpressFlow Engine contains the switching data base in-
terface and buffer management logic in order to do the switching
decision making for unicast, multicast, and broadcast frames.
Hardware assisted queue manager is incorporated to facilitate
buffer management. It also provides a generic Management Bus
interface to allow external processor to do initialization, learning,
VLAN, and RMON support, etc. In addition, a XpressFlow Bus
interface block is responsible for communicating with the Network
Access Controllers through the XpressFlow message passing
protocol.
Related Components:
t EA218E – 8-port 10Mbps Ethernet Access Controller
t EA218 – 6-port 10 + 2-port 10/100 Ethernet Access Controller
t EA234 – 4-port 10/100 Fast Ethernet


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