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SC220C5PTAV Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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SC220C5PTAV Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
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5 / 34 page  PRELIMINARY INFORMATION XpressFlow-2020 Series – SC220 Ethernet Switch Chipset XpressFlow Engine © 1998 Vertex Networks, Inc. 4 Rev. 4.5 – February 1999 1.2 Pin Assignment (Preliminary) Note: # Active low signal Input Input signal I-ST Input signal with Schmitt-Trigger Output Output signal (Tri-State driver) Out-OD Output signal with Open-Drain driver I/O-TS Input & Output signal with Tri-State driver I/O-OD Input & Output signal with Open-Drain driver 5VT Input with 5V Tolerance Pin No(s). Symbol Type Name & Functions XpressFlow Bus Interface 122,121,119,118, 116 S_D[31:27] / P_C[0:4] CMOS I/O-TS XpressFlow Bus – Data Bit [31:28] or Processor Interface Configuration Bit [0:4] 114,113,111,109,108, 106,105,104,103,101, 100,98,97,96,95,93,92, 90,89,88,87,85,84,82, 80,79,77 S_D[26:0] CMOS I/O-TS XpressFlow Bus – Data Bit [27:0] 71 S_MSGEN# CMOS I/O-TS XpressFlow Bus – Message Envelope 69 S_EOF# CMOS I/O-TS XpressFlow Bus – End of Frame 72 S_IRDY CMOS I/O-TS XpressFlow Bus – Initiator Ready 70 S_TABT# CMOS I/O-OD XpressFlow Bus – Target Abort 123 S_HPREQ# CMOS I/O-OD XpressFlow Bus – High Priority Request 140,138,135,133,131, 129,126,124 S_REQ[8:1]# CMOS Input ** XpressFlow Bus – Bus Request [8:1] 141,139,137,134,132, 130,128,125 S_GNT[8:1]# CMOS Output XpressFlow Bus – Bus Grant [8:1] 73 S_OVLD# CMOS Output XpressFlow Bus – Bus Overload 75 S_CLK CMOS Input XpressFlow Bus – Clock |
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