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M36D0R6040T0ZAIF Datasheet(PDF) 4 Page - STMicroelectronics |
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M36D0R6040T0ZAIF Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 18 page M36D0R6040T0, M36D0R6040B0 4/18 SUMMARY DESCRIPTION The M36D0R6040T0 and M36D0R6040B0 com- bine two memory devices in a Multi-Chip Package: a 64-Mbit, Multiple Bank Flash memory, the M58WR064FT/B, and a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating condi- tions do not allow more than one memory to be ac- tive at the same time. The memory is offered in a Stacked TFBGA67 (12 x 8mm, 8x8 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compli- ance with JEDEC Std J-STD-020B, the ST ECO- PACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free solder- ing processes. The memory is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names AI09200 22 A0-A21 DQ0-DQ15 M36D0R6040T M36D0R6040B GF 16 WF RPF WPF E1P GP WP UBP LBP VSS VDDF VPPF VDDP EF E2P A0-A19 Common Address Inputs DQ0-DQ15 Common Data Input/Output VDDF Flash Memory Power Supply VPPF Common Flash Optional Supply Voltage for Fast Program & Erase VSS Ground VDDP PSRAM Power Supply NC Not Connected Internally Flash Memory Signals A21-A20 Address Inputs for the Flash memory only EF Chip Enable input GF Output Enable input WF Write Enable input RPF Reset input WPF Write Protect input PSRAM Signals E1P Chip Enable input GP Output Enable input WP Write Enable input E2P Power-down input UBP Upper Byte Enable input LBP Lower Byte Enable input |
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