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TLE75602-ESD Datasheet(PDF) 12 Page - Infineon Technologies AG |
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TLE75602-ESD Datasheet(HTML) 12 Page - Infineon Technologies AG |
12 / 70 page Datasheet 12 Rev. 1.0 2017-11-23 TLE75602-ESD SPIDER+ 12V General Product Characteristics 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. 4.3.1 PCB set up Figure 5 2s2p PCB Cross Section Table 4 Thermal Resistance Parameter Symbol Values Unit Note or Test Condition Numbe r Min. Typ. Max. Junction to Soldering Point RthJSP –3 5 K/W 1) measured to exposed pad (pin 25) 1) not subject to production test, specified by design P_4.3.4 Junction to Ambient RthJA –28 – K/W 1)2) 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip+Package) was simulated on a 76.2 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.3.5 1.5mm 70µm 35µm 0.3mm Zth_PCB_2s2p.emf |
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