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STK14C88-M
April 1999
5-45
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
e
Note g:
W and HSB must be high during SRAM READ cycles.
Note h:
Device is continuously selected with E and G both low.
Note i:
Measured
± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
SRAM READ CYCLE #2: E Controlledg
NO.
SYMBOLS
PARAMETER
STK14C88-35M
STK14C88-45M
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
1tELQV
tACS
Chip Enable Access Time
35
45
ns
2tAVAV
g
tRC
Read Cycle Time
35
45
ns
3tAVQV
h
tAA
Address Access Time
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
15
20
ns
5tAXQX
h
tOH
Output Hold after Address Change
3
3
ns
6tELQX
tLZ
Chip Enable to Output Active
5
5
ns
7tEHQZ
tHZ
Chip Disable to Output Inactive
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
ns
9tGHQZ
i
tOHZ
Output Disable to Output Inactive
13
15
ns
10
tELICCH
tPA
Chip Enable to Power Active
0
0
ns
11
tEHICCL
tPS
Chip Disable to Power Standby
35
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
4
tGLQV
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
9
tGHQZ
10
tELICCH
11
tEHICCL
7
tEHQZ
8
tGLQX
E
DQ (DATA OUT)