TM497BBK32, TM497BBK32S

4194304 BY 32-BIT

DYNAMIC RAM MODULE

SMMS433B – JANUARY 1993 – REVISED JUNE 1995

6

POST OFFICE BOX 1443

capacitance over recommended ranges of supply voltage and operating free-air temperature,

f = 1 MHz (see Note 5)

PARAMETER

MIN

MAX

UNIT

Ci(A)

Input capacitance, address inputs

40

pF

Ci(R)

Input capacitance, RAS inputs

28

pF

Ci(C)

Input capacitance, CAS inputs

14

pF

Ci(W)

Input capacitance, write-enable input

56

pF

Co(DQ) Output capacitance on DQ pins

7

pF

NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature

PARAMETER

’497BBK32-60

’497BBK32-70

’497BBK32-80

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tAA

Access time from column address

30

35

40

ns

tCAC

Access time from CAS low

15

18

20

ns

tCPA

Access time from column precharge

35

40

45

ns

tRAC

Access time from RAS low

60

70

80

ns

tCLZ

CAS to output in low-impedance state

0

0

0

ns

tOH

Output disable time from start of CAS high

3

3

3

ns

tOFF

Output disable time after CAS high (see Note 6)

0

15

0

18

0

20

ns

NOTE 6: tOFF is specified when the output is no longer driven.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

’497BBK32-60

’497BBK32-70

’497BBK32-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tRC

Cycle time, random read or write (see Note 7)

110

130

150

ns

tPC

Cycle time, page-mode read or write (see Notes 7 and 8)

40

45

50

ns

tRASP

Pulse duration, page-mode, RAS low

60

100 000

70

100 000

80

100 000

ns

tRAS

Pulse duration, non-page-mode, RAS low

60

10 000

70

10 000

80

10 000

ns

tCAS

Pulse duration, CAS low

15

10 000

18

10 000

20

10 000

ns

tCP

Pulse duration, CAS high

10

10

10

ns

tRP

Pulse duration, RAS high (precharge)

40

50

60

ns

tWP

Pulse duration, W low

10

10

10

ns

tASC

Setup time, column address before CAS low

0

0

0

ns

tASR

Setup time, row address before RAS low

0

0

0

ns

tDS

Setup time, data before CAS low

0

0

0

ns

tRCS

Setup time, W high before CAS low

0

0

0

ns

tCWL

Setup time, W-low before CAS high

15

18

20

ns

tRWL

Setup time, W-low before RAS high

15

18

20

ns

tWCS

Setup time, W-low before CAS low

0

0

0

ns

tWRP

Setup time, W-high before RAS low (CBR refresh only)

10

10

10

ns

NOTES:

7. All cycles assume tT = 5 ns.

8. To assure tPC min, tASC should be ≥ tCP.