4

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

3.3V ABT 16-Bit Transparent D-Type Latches

54LVTH16373

12.19.01 Rev 1

1000603

Hold Current

I

I(HOLD)

V

V

Data

Inputs

75

--

µA

V

-75

--

Output Disabled Leakage

Current - High

I

OZH

V

--

5

µA

Output Disabled Leakage

Current - Low

I

OZL

V

--

-5

µA

Power Up Current

I

OZPU

2

V

--

±100

µA

Power Down Current

I

OZPD

2

V

--

±100

µA

Supply Current

I

CC

V

I

V

Outputs

high

--

0.19

mA

Outputs

low

--

5

Outputs

disabled

--

0.19

Delta Supply Current

CC

1

V

inputs at V

--

0.2

mA

Input Capacitance

C

I

2

V

--

10

pF

Input Output Capacitance

C

O

2

V

--

15

pF

1. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

2. Guaranteed by design.

(V

°

V

V

Pulse duration, LE high

t

W

3.3

--

3.3

--

ns

Setup time, data before LEØ

t

SU

0.5

--

0.5

--

ns

Hold time, data after LEØ

t

H

1.8

--

2

--

ns

Propagation Delay Time

D to Q

t

PLH

2.7

5

--

5.7

ns

t

PHL

2.9

4.9

--

5.7

Propagation Delay Time

LE to Q

t

PLH

3.6

6

--

6.8

ns

t

PHL

4.7

6.9

--

8.8

Output Enable Time

OE to Q

t

PZH

2.9

5.3

--

6.3

ns

t

PZL

35.1

--

5.9

(V

°