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AS7C252MNTF18A-85TQC Datasheet(PDF) 8 Page - Alliance Semiconductor Corporation |
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AS7C252MNTF18A-85TQC Datasheet(HTML) 8 Page - Alliance Semiconductor Corporation |
8 / 18 page ® AS7C252MNTF18A 1/17/05, v 1.1 Alliance Semiconductor P. 8 of 18 DC electrical characteristics † LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. *VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC **VIL min = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Sym Conditions Min Max Unit Input leakage current† |ILI|VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Input high (logic 1) voltage VIH Address and control pins 1.7* VDD+0.3 V I/O pins 1.7* VDDQ+0.3 V Input low (logic 0) voltage VIL Address and control pins -0.3** 0.7 V I/O pins -0.3** 0.7 V Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V Parameter Sym Conditions -75 -85 -10 Unit Operating power supply current1 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. ICC CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL 325 300 275 mA Standby power supply current ISB All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL 140 130 130 ISB1 Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V 90 90 90 ISB2 Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH 80 80 80 |
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