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AS7C252MPFS18A-200TQCN Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation

Part # AS7C252MPFS18A-200TQCN
Description  2.5V 2M x 18 pipelined burst synchronous SRAM
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C252MPFS18A-200TQCN Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation

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AS7C252MPFS18A
2/14/05, v.1.3
Alliance Semiconductor
6 of 18
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b;
BWE, BWn = internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function
GWE
BWE
BWa
BWb
Write All Bytes
LX
X
X
HL
L
L
Write Byte a
H
L
L
H
Write Byte b
H
L
H
L
Read
HH
XX
HLH
H
Operation
ZZ
OE
I/O Status
Snooze mode
H
X
High-Z
Read
L
L
Dout
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Interleaved burst address (LBO = 1)
Linear burst address (LBO = 0)
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
Starting Address
0 0
0 1
1 0
1 1
Starting Address
0 0
0 1
1 0
1 1
First Increment
0 1
0 0
1 1
1 0
First Increment
0 1
1 0
1 1
0 0
Second Increment
1 0
1 1
0 0
0 1
Second Increment
1 0
1 1
0 0
0 1
Third Increment
1 1
1 0
0 1
0 0
Third Increment
1 1
1 0
0 1
1 0


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