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AS7C251MNTF32A-85TQIN Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C251MNTF32A-85TQIN Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 18 page December 2004 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C251MNTF32A AS7C251MNTF36A 12/23/04, v 1.1 Alliance Semiconductor P. 1 of 18 2.5V 1M × 32/36 Flowthrough SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits •NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns •Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable control • Available in 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 2.5V core power supply • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic block diagram Selection guide -75 -85 -10 Units Minimum cycle time 8.5 10 12 ns Maximum clock access time 7.5 8.5 10 ns Maximum operating current 325 300 275 mA Maximum standby current 140 130 130 mA Maximum CMOS standby current (DC) 90 90 90 mA Address D Q CLK register Output Buffer DQ[a,b,c,d] 20 20 CLK CE0 CE1 CE2 A[19:0] OE CEN Control CLK logic Data D Q CLK Input Register 32/36 32/36 OE 1M x 32/36 SRAM Array R/W DQ[a,b,c,d] BWb BWd CLK Q D ADV / LD LBO Burst logic addr. registers Write delay 20 ZZ CLK 32/36 32/36 32/36 32/36 BWc BWa |
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