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AS7C3364NTD32B

AS7C3364NTD36B

4/28/05; v.1.3

Alliance Semiconductor

P. 4 of 19

Functional description

The AS7C3364NTD36B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM)

organized as 65,536 words × 32 or 36 bits and incorporates a LATE LATE Write.

write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data,

command, and address are all applied to the device on the same clock edge. If a read command follows this write command,

the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce

overall bandwidth for applications requiring random access or read-modify-write operations.

pipeline (flowthrough) read latency. Write data is applied two cycles after the write command and address, allowing the read

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full

32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is

applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled

for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-

selected by any of the three chip enable inputs (refer to synchronous truth table on page 6.) In pipeline mode, a two cycle

deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external

addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the

LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input.

14×20 mm TQFP package.

TQFP Capacitance

*Guranteed not tested

TQFP thermal resistance

Parameter

Symbol

Test conditions

Min

Max

Unit

Input capacitance

-

5

pF

I/O capacitance

-

7

pF

Description

Conditions

Symbol

Typical

Units

Thermal resistance

1 This parameter is sampled

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1–layer

40

°C/W

4–layer

22

°C/W

Thermal resistance

8

°C/W