AS7C1024B-20JCN datasheet(4/9 Pages) ALSC

Part #	AS7C1024B-20JCN

Description	5V 128K X 8 CMOS SRAM

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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4 / 9 page

AS7C1024B

3/26/04, v 1.2

Alliance Semiconductor

P. 4 of 9

®

Read cycle (over the operating range)3,9,12

Parameter

Symbol

-10

-12

-15

-20

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Read cycle time

tRC

10

-

12–15–20–

ns

Address access time

tAA

-

10–12–15–

20

ns

3

Chip enable (CE1) access time

tACE1

-

10–12–15–

20

ns

3, 12

Chip enable (CE2) access time

tACE2

-

10–12–15–

20

ns

3, 12

Output enable (OE) access time

tOE

-

5

–6

–7

–8

ns

Output hold from address change tOH

3

-

3–

ns

5

CE1 Low to output in low Z

tCLZ1

3

-

3

–

3

–

3

–

ns

4, 5, 12

CE2 High to output in low Z

tCLZ2

3

-

3

–

3

–

3

–

ns

4, 5, 12

CE1 Low to output in high Z

tCHZ1

-

4

–

5

–

6

–

7

ns

4, 5, 12

CE2 Low to output in high Z

tCHZ2

-

4

–

5

–

6

–

7

ns

4, 5, 12

OE Low to output in low Z

tOLZ

0

-

0–

ns

4, 5

OE High to output in high Z

tOHZ

–4

–5

–6

–7

ns

4, 5

Power up time

tPU

0

-

0

–

0

–

0

–

ns

4, 5, 12

Power down time

tPD

–10–12–15–

20

ns

4, 5, 12

Key to switching waveforms

Read waveform 1 (address controlled)3,6,7,9,12

Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12

Undefined / don’t care

Falling input

Rising input

Address

DOUT

Data valid

tOH

tAA

tRC

supply

Current

CE2

OE

DOUT

tOE

tOLZ

tACE1, tACE2

tCHZ1, tCHZ2

tCLZ1, tCLZ2

tPU

tPD

ICC

ISB

50%

Data valid

tRC1

CE1

tOHZ

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