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PCA9450 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCA9450 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 96 page  NXP Semiconductors PCA9450 Power management IC for i.MX 8M application processor family PCA9450 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 1.0 — 19 November 2019 9 / 96 7.3 Power modes PCA9450 has eight power modes: OFF, READY, SNVS, RUN, STADNBY, PWRDN, PWRUP and FAULT_SD. Figure 4 shows the state transition diagram showing the conditions to enter and exit each state. aaa-035703 PMIC_STBY_REQ = L OFF SNVS Run STANDBY Ready PWRDN Seq PWRUP Seq VSYS_POR = 0 VSYS_POR = 1 VSYS_UVLO = 0 VSYS_UVLO = 1 PMIC_ON_REQ = L Or Cold Reset PMIC_ON_REQ = H PMIC_STBY_REQ = H PMIC_ON_REQ = L Or Cold reset Any State VSYS_POR = 1 VSYS_UVLO = 1 FAULT_SD VR_FLT VR_FLT VR_FLT THSD = 0 or LDO1/2 FLT Clear VR_FLT Clear Figure 4. Power States Diagram 7.3.1 Off mode PCA9450 enters OFF mode from any state when VSYS falls below VSYS_POR threshold. All regulators are off and all registers get reset in this mode. 7.3.2 READY mode PCA9450 enters READY mode from OFF mode when VSYS is higher than VSYS_POR. Internal LDO VINT is enabled and loads Multiple Time Program (MTP) data to registers. Once MTP loading is done, it is ready to transition to SNVS mode. 7.3.3 SNVS mode PCA9450 enters Secure Non-Volatile Storage mode (SNVS) when VSYS exceeds VSYS_UVLO threshold. LDO1 and LDO2 are powered up and 32.768 kHz buffer starts running. RTC_RESET_B is pulled high in tRTC_RST after both LDO1 and LDO2 voltage come up. PMIC_ON_REQ input is masked until RTC_RESET_B is released. PCA9450 starts power up sequence if PMIC_ON_REQ is asserted high in this mode. |
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