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IDT71V3559S80PFI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V3559S80PFI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 28 page  OCTOBER 2004 DSC-5282/07 1 ©2004 Integrated Device Technology, Inc. 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Pin Description Summary it read or write. The IDT71V3557/59 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable ( CEN) pin allows operation of the IDT71V3557/59 to be suspended as long as necessary. All synchronous inputs are ignored when ( CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins ( CE1,CE2,CE2) that allow the user todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted when ADV/ LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after chip is de- selected or a write is initiated. The IDT71V3557/59 have an on-chip burst counter. In the burst mode, the IDT71V3557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/ LD signal is used to load a new externaladdress(ADV/ LD=LOW)orincrementtheinternalburstcounter (ADV/ LD = HIGH). The IDT71V3557/59 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). Features x x x x x 128K x 36, 256K x 18 memory configurations x x x x x Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) x x x x x ZBTTM Feature - No dead cycles between write and read cycles x x x x x Internally synchronized output buffer enable eliminates the need to control OE OE OE OE OE x x x x x Single R/ W W W W W (READ/WRITE) control pin x x x x x 4-word burst capability (Interleaved or linear) x x x x x Individual byte write ( BW BW BW BW BW1 - BW BW BW BW BW4) control (May tie active) x x x x x Three chip enables for simple depth expansion x x x x x 3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ) x x x x x Optional Boundary Scan JTAG Interface (IEEE 1149.1 complaint) x x x x x Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega- bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. AddressandcontrolsignalsareappliedtotheSRAMduringoneclock cycle, and on the next clock cycle the associated data cycle occurs, be A0-A17 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/ W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/ LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5282 tbl 01 IDT71V3557S IDT71V3559S IDT71V3557SA IDT71V3559SA |
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