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DRV8714-Q1 Datasheet(PDF) 16 Page - Texas Instruments |
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DRV8714-Q1 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 144 page  4.9 V ≤ VPVDD ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V and TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tBLK, SPI Sense amplifier output blanking time SPI Device CSA_BLK = 000b, % of tDRIVE period 0 % CSA_BLK = 001b, % of tDRIVE period 25 CSA_BLK = 010b, % of tDRIVE period 37.5 CSA_BLK = 011b, % of tDRIVE period 50 CSA_BLK = 100b, % of tDRIVE period 62.5 CSA_BLK = 101b, % of tDRIVE period 75 CSA_BLK = 110b, % of tDRIVE period 87.5 CSA_BLK = 111b, % of tDRIVE period 100 tBLK, H/W Sense amplifier output blanking time H/W Device 0 ns tSLEW Output slew rate CSO = 60 pF 5 V/µs VBIAS, SPI Output voltage bias SPI Device VSPx = VSNx = 0 V, CSA_DIV = 0b VAREF / 2 V VSPx = VSNx = 0 V, CSA_DIV = 1b VAREF / 8 VBIAS, H/W Output voltage bias H/W Device VAREF / 2 V VLINEAR Linear output voltage range VAREF = 3.3 V = 5 V 0.25 VAREF – 0.25 V VOFF Input offset voltage VSPx = VSNx = 0 V, TJ = 25℃ –1.5 1.5 mV VOFF_D Input offset voltage drift VSPx = VSNx = 0 V ±10 ±25 µV/ ℃ IBIAS Input bias current VSPx = VSNx = 0 V 100 µA IBIAS_OFF Input bias current offset ISPx – ISNx –1 1 µA IAREF AREF input current VVREF = 3.3 V = 5 V DRV8718-Q1 RVJ, DRV8714-Q1 RVJ 2 3 mA CMRR Common mode rejection ratio DC 75 100 dB 20kHz 80 PSRR Power supply rejection ratio PVDD to SOx, DC 120 dB PVDD to SOx, 20kHz 90 PVDD to SOx, 400kHz 80 PROTECTION CIRCUITS VPVDD_UV PVDD undervoltage threshold VPVDD rising 4.325 4.625 4.9 V VPVDD falling 4.25 4.525 4.8 VPVDD_UV_H YS PVDD undervoltage hysteresis Rising to falling threshold 100 mV tPVDD_UV_DG PVDD undervoltage deglitch time 8 10 12.75 µs VPVDD_OV PVDD overvoltage threshold VPVDD rising, PVDD_OV_LVL = 0b 21 22.5 24 V VPVDD falling, PVDD_OV_LVL = 0b 20 21.5 23 VPVDD rising, PVDD_OV_LVL = 1b 27 28.5 30 VPVDD falling, PVDD_OV_LVL = 1b 26 27.5 29 VPVDD_OV_H YS PVDD overvoltage hysteresis Rising to falling threshold 1 V tPVDD_OV_DG PVDD overvoltage deglitch time PVDD_OV_DG = 00b 0.75 1 1.5 µs PVDD_OV_DG = 01b 1.5 2 2.5 PVDD_OV_DG = 10b 3.25 4 4.75 PVDD_OV_DG = 11b 7 8 9 VDVDD_POR DVDD supply POR threshold DVDD falling 2.5 2.7 2.9 V DVDD rising 2.6 2.8 3 DRV8714-Q1, DRV8718-Q1 SLVSEA2 – AUGUST 2020 www.ti.com 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DRV8714-Q1 DRV8718-Q1 |
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