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DRV8889-Q1 Datasheet(PDF) 35 Page - Texas Instruments |
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DRV8889-Q1 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 88 page  typical), nFAULT pin is released (is pulled-up to the external voltage), and the FAULT bit is reset, but the UVLO bit remains latched high until cleared through the CLR_FLT bit or an nSLEEP reset pulse. When the voltage on the VM pin falls below the VM UVLO reset voltage (VRST, 3.9 V maximum), SPI communication is unavailable, the digital core is shutdown, the FAULT and UVLO bits are low and the nFAULT pin is high. During the subsequent power-up, when the VM voltage exceeds the VRST voltage, the digital core comes alive, UVLO bit stays low but the FAULT bit is made high; and the nFAULT pin is pulled low, as shown in Figure 7-20. When the VM voltage exceeds the VM UVLO rising threshold, FAULT bit is reset, UVLO bit stays low and the nFAULT pin is pulled high. 7.3.11.2 VCP Undervoltage Lockout (CPUV) If at any time the voltage on the VCP pin falls below the CPUV voltage, all the outputs are disabled, and the nFAULT pin is driven low. The charge pump remains active during this condition. The FAULT and CPUV bits are made high in the SPI registers. Normal operation resumes (motor-driver operation starts, nFAULT released and FAULT bit is made low) when the VCP undervoltage condition is removed. The CPUV bit remains set until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse. 7.3.11.3 Overcurrent Protection (OCP) An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this current limit persists for longer than the tOCP time, the FETs in that particular H-bridge are disabled and the nFAULT pin is driven low. The FAULT and OCP bits are latched high in the SPI registers. For xOUTx to VM short, corresponding OCP_LSx_x bit goes high in the DIAG Status 1 register. Similarly, for xOUTx to ground short, corresponding OCP_HSx_x bit goes high. For example, for AOUT1 to VM short, OCP_LS1_A bit goes high; and for BOUT2 to ground short, the OCP_HS2_B bit goes high. The charge pump remains active during this condition. The overcurrent protection can operate in two different modes: latched shutdown and automatic retry. 7.3.11.3.1 Latched Shutdown (OCP_MODE = 0b) In this mode, after an OCP event, the relevant outputs are disabled and the nFAULT pin is driven low. Normal operation resumes after sending a CLR_FLT command, or an nSLEEP reset pulse or a power cycling. This is the default mode for an OCP event for the device. 7.3.11.3.2 Automatic Retry (OCP_MODE = 1b) In this mode, after an OCP event, the relevant outputs are disabled and the nFAULT pin is driven low. Normal operation resumes automatically (motor-driver operation starts, nFAULT released and FAULT bit goes low) after the tRETRY time has elapsed and the fault condition is removed. 7.3.11.4 Open-Load Detection (OL) If the winding current in any coil drops below the open load current threshold (IOL) and the ITRIP level set by the indexer, and if this condition persists for more than the open load detection time (tOL), an open-load condition is detected. The EN_OL bit must be '1' to enable open load detection. When an open load fault is detected, the OL and FAULT bits are latched high in the SPI register and the nFAULT pin is driven low. If the OL_A bit is high, it indicates an open load fault in winding A, between AOUT1 and AOUT2. Similarly, an open load fault between BOUT1 and BOUT2 causes the OL_B bit to go high. Normal operation resumes and the nFAULT line is released when the open load condition is removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. The fault also clears when the device is power cycled or comes out of sleep mode. If the motor is held at a position corresponding to 0°, 90°, 180° or 270° electrical angles, for more than the open load detection time, open load fault will be flagged, as one of the coil current is zero. This situation does not arise in full-step mode, because the coil currents are never zero. 7.3.11.5 Stall Detection Stepper motors have a distinct relation between the winding current, back-EMF, and mechanical torque load of the motor, as shown in Figure 7-21. As motor load approaches the torque capability of the motor at a given winding current, the back-EMF will move in phase with the winding current. By detecting back-emf phase shift www.ti.com DRV8889-Q1 SLVSEE9C – APRIL 2020 – REVISED AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DRV8889-Q1 |
Similar Part No. - DRV8889-Q1_V02 |
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Similar Description - DRV8889-Q1_V02 |
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