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LMK61E08 Datasheet(PDF) 37 Page - Texas Instruments |
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LMK61E08 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 54 page  37 LMK61E08 www.ti.com SNAS805 – JUNE 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 8.6.1.33 NVMLCRC Register; R50 The NVMLCRC register holds the Live CRC (Cyclic Redundancy Check) byte. BIT NO. FIELD TYPE DEFAUL T EEPROM DESCRIPTION [7:0] NVMLCRC[7:0] R 0x00 N EEPROM Live CRC. 8.6.1.34 MEMADR Register; R51 The MEMADR register holds 7-bits of the starting address for on-chip SRAM or EEPROM access. BIT NO. FIELD TYPE DEFAU LT EEPROM DESCRIPTION [7] RESERVED - - N Reserved. [6:0] MEMADR[6:0] RW 0x00 N Memory Address. The MEMADR value determines the starting address for on-chip SRAM read/write access or on-chip EEPROM access. The internal address to access SRAM or EEPROM is automatically incremented; however the MEMADR register does not reflect the internal address in this way. When the SRAM or EEPROM arrays are accessed using the I2C interface only bits [4:0] of MEMADR are used to form the byte Wise address. 8.6.1.35 NVMDAT Register; R52 The NVMDAT register returns the on-chip EEPROM contents from the starting address specified by the MEMADR register. BIT NO. FIELD TYPE DEFAUL T EEPROM DESCRIPTION [7:0] NVMDAT[7:0] - - N Reserved. 8.6.1.36 RAMDAT Register; R53 The RAMDAT register provides read and write access to the SRAM that forms part of the on-chip EEPROM module. BIT NO. FIELD TYPE DEFAUL T EEPROM DESCRIPTION [7:0] RAMDAT[7:0] - - N Reserved. 8.6.1.37 NVMUNLK Register; R56 The NVMUNLK register provides a rudimentary level of protection to prevent inadvertent programming of the on- chip EEPROM. BIT NO. FIELD TYPE DEFAUL T EEPROM DESCRIPTION [7:0] NVMUNLK[7:0] RW 0x00 N EEPROM Prog Unlock. The NVMUNLK register must be written immediately prior to setting the NVMPROG bit of register NVMCTL, otherwise the Erase/Program cycle will not be triggered. NVMUNLK must be written with a value of 0xBE. |
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