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AS7C33512NTD18A-133TQC Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS7C33512NTD18A-133TQC Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
9 / 19 page ® AS7C33512NTD18A 11/30/04; v.2.1 Alliance Semiconductor 9 of 19 Timing characteristics over operating range for 3.3V I/O Parameter Symbol –166 –133 Unit Notes1 1 Refer to “notes” on page 16. Min Max Min Max Clock frequency fMax –166–133 MHz Cycle time tCYC 6– 7.5 – ns Clock access time tCD –3.5–4.0 ns Output enable LOW to data valid tOE –3.5–4.0 ns Clock HIGH to output Low Z tLZC 0 – 0 – ns 2,3,4 Data output invalid from clock HIGH tOH 1.5–1.5 – ns 2 Output enable LOW to output Low Z tLZOE 0 – 0 – ns 2,3,4 Output enable HIGH to output High Z tHZOE – 3.5 – 4.0 ns 2,3,4 Clock HIGH to output High Z tHZC – 3.5 – 4.0 ns 2,3,4 Output enable HIGH to invalid output tOHOE 0– 0– ns Clock HIGH pulse width tCH 2.4–2.5 – ns 5 Clock LOW pulse width tCL 2.4–2.5 – ns 5 Address setup to clock HIGH tAS 1.5–1.5 – ns 6 Data setup to clock HIGH tDS 1.5–1.5 – ns 6 Write setup to clock HIGH tWS 1.5 – 1.5 – ns 6,7 Chip select setup to clock HIGH tCSS 1.5 – 1.5 – ns 6,8 Address hold from clock HIGH tAH 0.5–0.5 – ns 6 Data hold from clock HIGH tDH 0.5–0.5 – ns 6 Write hold from clock HIGH tWH 0.5 – 0.5 – ns 6,7 Chip select hold from clock HIGH tCSH 0.5 – 0.5 – ns 6,8 Clock enable setup to clock HIGH tCENS 1.5–1.5 – ns 6 Clock enable hold from clock HIGH tCENH 0.5–0.5 – ns 6 ADV/LD setup to clock HIGH tADVS 1.5–1.5 – ns 6 ADV/LD hold from clock HIGH tADVH 0.5–0.5 – ns 6 |
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