®

AS7C33512NTD18A

11/30/04;

v.2.1

Alliance Semiconductor

5 of 19

Snooze Mode

duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not

guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid

should be given while the SRAM is transitioning out of SNOOZE MODE.

Signal descriptions

Signal

I/O Properties

Description

CLK

I

CLOCK

Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.

CEN

I

SYNC

Clock enable. When de-asserted HIGH, the clock input signal is masked.

A, A0, A1

I

SYNC

Address. Sampled when all chip enables are active and ADV/LD is asserted.

DQ[a,b]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0, CE1,

CE2

I

SYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.

Are ignored when ADV/LD is HIGH.

ADV/LD

I

SYNC

Advance or Load. When sampled HIGH, the internal burst address counter will increment

in the order defined by the LBO input value. (refer to table on page 2) When LOW, a new

address is loaded.

R/W

I

SYNC

A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a

WRITE operation. Is ignored when ADV/LD is HIGH.

BW[a,b]

I

SYNC

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE

command and BURST WRITE.

OE

I

ASYNC

Asynchronous output enable. I/O pins are not driven when OE is inactive.

LBO

ISTATIC

order. When driven Low, device follows linear Burst order. This signal is internally pulled

High.

ZZ

I

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.

NC

-

-

No connects. Note that pin 84 will be used for future address expansion to 18Mb density.