July 2005

ASM2I99446

rev 0.4

2.5V and 3.3V LVCMOS Clock Distribution Buffer

5 of 14

Notice: The information in this document is subject to change without notice.

1

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input Frequency

0

250

2

MHz

Maximum Output Frequency

÷1 output

÷2 output

0

0

250

2

125

MHz

MHz

FSELx=0

FSELx=1

Reference Input Pulse Width

1.4

nS

CCLK Input Rise/Fall Time

1.0

3

nS

0.8 to 2.0V

Propagation delay

CCLK0,1 to any Q

CCLK0,1 to any Q

2.2

2.2

2.8

2.8

4.45

4.2

nS

nS

Output Disable Time

10

nS

Output Enable Time

10

nS

Output-to-output Skew

Within one bank

Any output Bank, Same output divider

Any output, Any output divider

150

200

350

pS

pS

pS

Device-to-device Skew

2.25

nS

Output pulse skew

4

200

pS

Output Duty Cycle

÷1 output

÷2 output

47

45

50

50

53

55

%

%

Output Rise/Fall Time

0.1

1.0

nS

0.55 to 2.4V

2 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.

3 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input High Voltage

1.7

V

LVCMOS

Input Low Voltage

-0.3

0.7

V

LVCMOS

Output High Voltage

1.8

V

1

Output Low Voltage

0.6

V

Output Impedance

17 - 20

2

Ω

Input Current

2

±200

µA

3

Maximum Quiescent Supply Current

2.0

mA

Note: 1 The ASM2I99446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to

2 Input pull-up / pull-down resistors influence input current.