July 2005

ASM2I99446

rev 0.4

2.5V and 3.3V LVCMOS Clock Distribution Buffer

3 of 14

Notice: The information in this document is subject to change without notice.

Table 1: Pin Configuration

Pin Number

Pin

I/O

Type

Function

3,4

CCLK0, CCLK1

Input

LVCMOS

LVCMOS clock inputs

5,6,7

FSELA, FSELB, FSELC

Input

LVCMOS

Output bank divide select input

32

MR/OE

Input

LVCMOS

Internal reset and output (high impedance)

control

8,11,15,20,24,27,31

GND

-

Supply

Negative voltage supply (GND)

25,29

18,22

9,13,17

-

Supply

Positive voltage supply for output banks

2

-

Supply

30,28, 26

QA0 - QA2

Output

LVCMOS

Bank A outputs

23,21,19

QB0 - QB2

Output

LVCMOS

Bank B outputs

10,12,14,16

QC0 - QC3

Output

LVCMOS

Bank C outputs

Table 2: Supported Single and Dual Supply Configurations

Supply voltage configuration

1

2

3

4

GND

3.3V

3.3V

3.3V

3.3V

3.3V

0V

Mixed voltage supply

3.3V

3.3V or 2.5V

3.3V

3.3V or 2.5V

0 V

2.5V

2.5V

2.5V

2.5V

2.5V

0 V

Table 3: Function Table (Controls)

Control

Default

0

1

CCLK_SEL

0

CCLK0

CCLK1

FSELA

0

FSELB

0

FSELC

0

MR/OE

0

Outputs enabled

Internal reset Outputs disabled (tristate)

Table 4: Absolute Maximum Ratings

1

Symbol

Characteristics

Min

Max

Unit

Condition

Supply Voltage

-0.3

3.6

V

DC Input Voltage

-0.3

V

DC Output Voltage

-0.3

V

DC Input Current

±20

mA

DC Output Current

±50

mA

Storage temperature

-65

125

°C

Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.