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ASM2I99456 Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
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ASM2I99456 Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
6 / 14 page June 2005 ASM2I99456 rev 0.2 3.3V/2.5V LVCMOS Clock Fanout Buffer 6 of 14 Notice: The information in this document is subject to change without notice. Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, T A = –40 to +85°C) 1 Symbol Characteristics Min Typ Max Unit Condition fref Input Frequency 0 250 2 MHz fMAX Maximum Output Frequency ÷1 output ÷2 output 0 0 250 2 125 MHz MHz FSELx=0 FSELx=1 VPP Peak-to-peak input voltage PCLK 500 1000 mV LVPECL VCMR 3 Common Mode Range PCLK 1.1 VCC-0.7 V LVPECL tP, REF Reference Input Pulse Width 1.4 nS tr, tf PCLK Input Rise/Fall Time 1.0 4 nS 0.7 to 1.7V tPLH tPHL Propagation delay PCLK to any Q PCLK to any Q 2.6 2.6 5.6 5.5 nS nS tPLZ, HZ Output Disable Time 10 nS tPZL, LZ Output Enable Time 10 nS tsk(O) Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider 150 200 350 pS pS pS tsk(PP) Device-to-device Skew 3.0 nS tSK(P) Output pulse skew 5 200 pS DCQ Output Duty Cycle ÷1 or ÷2 output 45 50 55 % DCREF = 50% tr, tf Output Rise/Fall Time 0.1 1.0 nS 0.6 to 1.8V Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz. 3 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. 4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 5 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. Table 10. AC Characteristics (VCC = 3.3V ± 5%, VCCA = VCCB = VCCC = 2.5V ± 5% or 3.3V ± 5%,T A = –40 to +85°C) ,1,2 Symbol Characteristics Min Typ Max Unit Condition tsk(O) Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider 150 250 350 pS pS pS tsk(PP) Device-to-device Skew 2.5 nS tPLH,HL Propagation delay PCLK to any Q See 3.3V table tSK(P) Output pulse skew 3 250 pS DCQ Output Duty Cycle ÷1 or ÷2 output 45 50 55 % DCREF = 50% Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. 3 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. |
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