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ASM2I99448G-32-LR Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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ASM2I99448G-32-LR Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 15 page May 2005 ASM2I99448 rev 0.3 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer 2 of 15 Notice: The information in this document is subject to change without notice. Block Diagram Pin Diagram Table 1. FUNCTION TABLE Control Default 0 1 CLK_SEL 1 PECL differential input selected CCLK input selected OE 1 Outputs disabled (high-impedance state) 1 Outputs enabled CLK_STOP 1 Outputs synchronously stopped in logic low state Outputs active Note: 1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP. Q3 VCC Q2 GND Q1 VCC Q0 GND GND 25 24 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Q8 VCC Q9 GND Q10 VCC Q11 ASM2I99448 Q0 Q1 CLK PCLK Q3 Q4 Q5 STOP 0 1 VCC CCLK CLK_SEL SYNC VCC VCC CLK_STOP Q6 Q7 Q8 Q9 OE (All input resistors have a value of 25KΩ) VCC Q2 Q10 Q11 PCLK |
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