June 2005

ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer

6 of 14

Notice: The information in this document is subject to change without notice.

1

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input Frequency

0

250

2

MHz

Maximum Output Frequency

÷1 output

÷2 output

0

0

250

2

125

MHz

MHz

FSELx=0

FSELx=1

Peak-to-peak input voltage

PCLK

500

1000

mV

LVPECL

3

Common Mode Range

PCLK

1.1

VCC-0.7

V

LVPECL

Reference Input Pulse Width

1.4

nS

PCLK Input Rise/Fall Time

1.0

4

nS

0.7 to 1.7V

Propagation delay

PCLK to any Q

PCLK to any Q

2.6

2.6

5.6

5.5

nS

nS

Output Disable Time

10

nS

Output Enable Time

10

nS

Output-to-output Skew

Within one bank

Any output bank, same output divider

Any output, Any output divider

150

200

350

pS

pS

pS

Device-to-device Skew

3.0

nS

Output pulse skew

5

200

pS

Output Duty Cycle

÷1 or ÷2 output

45

50

55

%

Output Rise/Fall Time

0.1

1.0

nS

0.6 to 1.8V

2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.

4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

,1,2

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Output-to-output Skew

Within one bank

Any output bank, same output divider

Any output, Any output divider

150

250

350

pS

pS

pS

Device-to-device Skew

2.5

nS

Propagation delay

PCLK to any Q

See 3.3V table

Output pulse skew

3

250

pS

Output Duty Cycle

÷1 or ÷2 output

45

50

55

%

2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.