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ASM2I3805DG-20-DR Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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ASM2I3805DG-20-DR Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 12 page June 2005 ASM2P3805X rev 0.2 3.3V CMOS Dual 1-To-5 Clock Driver 2 of 12 Notice: The information in this document is subject to change without notice. Pin Description Pin # Pin Names Description 9,12 OE ¯¯ A, OE ¯¯ B 3-State Output Enable Inputs (Active LOW) 10,11 INA, INB Clock Inputs 2,3,4,6,7 OA1-OA5 Clock Outputs from Bank A 19,18,17,15,14 OB1-OB5 Clock Outputs from Bank B 1 VCCA Power supply for Bank A 20 VCCB Power supply for Bank B 5 GNDA Ground for Bank A 16 GNDB Ground for Bank B 8 GNDQ Ground 13 MON Monitor Output Function Table 1 Inputs Outputs OE ¯¯ A, OE ¯¯ B INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H Note: 1 H = HIGH; L = LOW; Z = High-Impedance Capacitance (T A = +25°C, f = 1.0MHz) Symbol Parameter 1 Conditions Typ Max Unit CIN Input Capacitance VIN= 0V 3 4 pF COUT Output Capacitance VOUT = 0V — 6 pF Note: 1 This parameter is measured at characterization but not tested. |
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