ASM2I3805AG-20-DR datasheet(6/13 Pages) ALSC

Part #	ASM2I3805AG-20-DR

Description	3.3V CMOS Buffer Clock Driver

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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6 / 13 page

June 2005

ASM2P3805AH

rev 0.2

3.3V CMOS Buffer Clock Driver

6 of 13

Notice: The information in this document is subject to change without notice.

Switching Characteristics Over Operating Range – Commercial

3,4

ASM2P3805A

ASM2P3805AH

Symbol

Parameter

Conditions

1

Min

2

Max

Min

2

Max

Unit

tPLH

tPHL

Propagation Delay

INA to OAn, INB to OBn

1.5

5.8

1.5

5

nS

tR

Output Rise Time (0.8V to 2.0V)

-

2

-

2

nS

tF

Output Fall Time (2.0V to 0.8V)

-

2

-

2

nS

tSK(O)

Output skew: skew between outputs of all

banks of same package

(inputs tied together)

-

0.5

-

0.5

nS

tSK(P)

Pulse skew: skew between opposite

transitions of same output (|tPHL -– tPLH|)

-

1

-

1

nS

tSK(T)

Package skew: skew between outputs of

different packages at same power supply

voltage, temperature, package type and

speed grade

-

1.5

-

1.2

nS

tPZL

tPZH

Output Enable Time

OE

¯¯ A to OAn, OE

¯¯ B to OBn

1.5

6.5

1.5

6

nS

tPLZ

tPHZ

Output Disable Time

OE

¯¯ A to OAn, OE

¯¯ B to OBn

CL= 50pF

RL= 500Ω

1.5

5.5

1.5

5

nS

Switching Characteristics Over Operating Range – Industrial

3,4

ASM2P3805A

ASM2P3805AH

Symbol

Parameter

Conditions

1

Min

2

Max

Min

2

Max

Unit

tPLH

tPHL

Propagation Delay

INA to OAn, INB to OBn

1.5

5.8

1.5

5.2

nS

tR

Output Rise Time (0.8V to 2.0V)

-

2

-

2

nS

tF

Output Fall Time (2.0V to 0.8V)

-

2

-

2

nS

tSK(O)

Output skew: skew between outputs of all

banks of same package (inputs tied

together)

-

0.6

-

0.6

nS

tSK(P)

Pulse skew: skew between opposite

transitions of same output (|tPHL -– tPLH|)

-

1

-

1

nS

tSK(T)

Package skew: skew between outputs of

different packages at same power supply

voltage, temperature, package type and

speed grade

-

1.5

-

1.2

nS

tPZL

tPZH

Output Enable Time

OE

¯¯ A to OAn, OE

¯¯ B to OBn

1.5

6.5

1.5

6

nS

tPLZ

tPHZ

Output Disable Time

OE

¯¯ A to OAn, OE

¯¯ B to OBn

CL= 50pF

RL= 500Ω

1.5

5.5

1.5

5

nS

Note: 1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.

4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay

limits do not imply skew.

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ASM2I3805AG-20-DR Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation

ASM2I3805AG-20-DR Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation

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