ASM3P2508SP-08ST datasheet(1/7 Pages) ALSC

Part #	ASM3P2508SP-08ST

Description	Clock Synthesizer and Frequency Generator with Peak EMI reduction

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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February 2005

ASM3P2508SP

rev 0.4

Alliance Semiconductor

2575, Augustine Drive

• Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

Clock Synthesizer and Frequency Generator with Peak EMI reduction

Features

Dual PLL based Architecture

Operates with a 3.3V ±0.3V supply.

Generates an EMI optimized Spread Spectrum

PCI Clock output

Generates a high accuracy non Spread T1 clock of

±25ppm accuracy.

Generates a non spread system reference clock

Low power CMOS design.

Input frequency: 25 MHz.

Outputs:

Sys_ REF_CLK: 20 MHz

T1 Clock: 25 MHz (±25 ppm)

PCI_CLK: 33.33MHz Spread Spectrum

Frequency deviation: -0.5% (Typ).

Available in 8L SOIC Package.

Product Description

The ASM3P2508SP is a versatile Dual PLL based Clock

Synthesizer and Frequency Generator optimised and

designed specifically for three clock frequencies. The

PCI_CLK

output

from

ASM3P2508SP

reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of all clock

dependent signals. ASM3P2508SP allows significant

system cost savings by reducing the number of circuit

board layers, ferrite beads & shielding that are

traditionally required to pass EMI regulations.

The ASM3P2508SP uses the most efficient and

optimized modulation profile approved by the FCC.

ASM3P2508SP modulates the output of a PLL in order to

“spread” the bandwidth of a synthesized clock, and more

importantly, decreases the peak amplitudes of its

harmonics. This results in a significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’ (SSCG).

In addition to the SSCG output, ASM3P2508SP

generates two high accuracy clock signals -

T1 Clock @ 25.00MHz with +/- 25ppm stability, and a

20MHz Sys_ REF_CLK.

Applications

The ASM3P2508SP is targeted towards Consumer,

Industrial, Data and Telecommunications applications.

Key Specifications

Description

Specification

Supply voltages

VDD = 3.3V ±0.3V

Input Frequency

25 MHz

Cycle-to-Cycle Jitter

175 pS ( Max)

Output Duty Cycle

45/55%

Output Rise and Fall Time

1.1 nS (Max)

SSC Modulation Rate

30KHz (Typ)

SSC Frequency Deviation

-0.5% (Typ)

Block Diagram

VSS

T1_CLK

Sys_REF_CLK

VDD

Modulation

XIN/CLKIN

Input

Divider

Osc

PLL 1

Output

Divider

PLL 2

PCI_CLK

XOUT

Output

Divider

PWRDNB

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ASM3P2508SP-08ST Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

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