Subject to Change without Notice
SiI 141B PanelLink
®
Digital Receiver
May 2001
General Description
Features
The SiI 141B uses PanelLink Digital technology to support displays
ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements.
These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
• Scaleable Bandwidth: 25-86 MHz (VGA to High
Refresh XGA)
• Low Power: 3.3V core operation & power-down mode
• Automatic power down when clock is inactive
• High Skew Tolerance: 1 full input clock cycle (15ns at
65 MHz)
• Pin-compatible with SiI 101, SiI 141
• Sync Detect: for Plug & Display “Hot Plugging”
• Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&D
TM and DFP)
SiI 141B Pin Diagram
1
SiI141B
80-Pin TQFP
(Top View)
PD
2
PDO
3
OGND
4
PIXS
5
DFO
6
SCDT
7
CTL1
8
CTL2
9
CTL3
10
GND
11
HSYNC
12
OGND
13
VSYNC
14
OVCC
15
Q0
16
56
Q30
55
Q29
54
Q28
53
Q27
52
Q26
51
VCC
50
Q25
49
OVCC
48
Q24
47
OGND
46
Q23
45
Q22
44
Q21
43
Q20
42
DE
41
Q31
8-bit Channel 0 Data
1-pixel/clock
24-bit Input Data for 1-pixel/clock mode
DIFFERENTIAL SIGNAL
8-bit Channel 1 Data
1-pixel/clock
MISC.
Q1
17
Q2
18
Q3
19
Q4
20
60
Q34
59
Q33
58
Q32
57
Q35
8-bit Channel 2 Data
1-pixel/clock
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
6-bit Odd Channel 0
Data 2-pixel/clock
18-bit Even Data for 2-pixel/clock mode
RESERVED
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