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COP8ACC528M8 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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COP8ACC528M8 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 43 page DC Electrical Characteristics (Continued) −40˚C ≤ T A ≤ +85˚C unless otherwise specified [OTP Value] Parameter Conditions Min Typ Max Units Input Capacitance (Note 14) 7 pF Load Capacitance on D2 (Note 14) 1000 pF AC Electrical Characteristics −40˚C ≤ T A ≤ +85˚C unless otherwise specified [OTP Value] Parameter Conditions Min Typ Max Units Instruction Cycle Time (t C) Crystal, Resonator 2.5V, [2.7V] ≤ V CC < 4V 2.5 DC µs 4V ≤ V CC ≤ 5.5V 1.0 DC µs R/C Oscillator 2.5V, [2.7V] ≤ V CC < 4V 7.5 DC µs 4V ≤ V CC < 5.5V 3.0 DC µs Inputs t SETUP 4V ≤ V CC ≤ 5.5V 200 ns 2.5V, [2.7V] ≤ V CC < 4V 500 ns t HOLD 4V ≤ V CC ≤ 5.5V 60 ns 2.5V, [2.7V] ≤ V CC < 4V 150 ns Output Propagation Delay (Note 14) R L = 2.2k, CL = 100 pF t PD1,tPD0 SO, SK 4V ≤ V CC ≤ 5.5V 0.7 µs 2.5V, [2.7V] ≤ V CC < 4V 1.75 µs All Others 4V ≤ V CC ≤ 5.5V 1 µs 2.5V, [2.7V] ≤ V CC < 4V 2.5 µs MICROWIRE Setup Time (t UWS) (Note 14) V CC ≥ 4V 20 ns MICROWIRE Hold Time (t UWH) (Note 14) V CC ≥ 4V 56 ns MICROWIRE Output Propagation Delay (t UPD)VCC ≥ 4V 220 ns Input Pulse Width (Note 15) Interrupt Input High Time 1 t C Interrupt Input Low Time 1 t C Timer 1, 2, 3 Input High Time 1 t C Timer 1, 2, 3 Input Low Time 1 t C Reset Pulse Width 1 µs Note 10: Maximum rate of voltage change must be < 0.5 V/ms. Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 12: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing or sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode. Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 14: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 15: Parameter characterized but not tested. Note 16: tC = Instruction Cycle Time. www.national.com 7 |
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