8
April 7, 2005
UL631H256
n: The software sequence is clocked with E controlled READs
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r:
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
No. Software Controlled STORE/RECALL
Cyclel, n
Symbol
35
45
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
25 STORE/RECALL Initiation Time
tAVAV
tcR
35
45
ns
26 Chip Enable to Output Inactiveo
tELQZ
tdis(E)SR
600
600
ns
27 STORE Cycle Timep
tELQXS
td(E)S
10
10
ms
28 RECALL Cycle Timeq
tELQXR
td(E)R
20
20
ms
29 Address Setup to Chip Enabler
tAVELN
tsu(A)SR
00
ns
30 Chip Enable Pulse Widthr, s
tELEHN
tw(E)SR
25
30
ns
31 Chip Disable to Address Changer
tEHAXN
th(A)SR
00
ns
Software Controlled STORE/RECALL Cyclet, u (E = HIGH after STORE initiation)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
Ai
E
DQi
Output
tcR
tsu(A)SR
tw(E)SR
High Impedance
ADDRESS 1
VALID
VALID
ADDRESS 6
tcR
td(E)S
tdis(E)SR (26)
(25)
(25)
(31)
(30)
(29)
(27)
(28)
th(A)SR
Ai
E
DQi
Output
tcR
tw(E)SR
High Impedance
ADDRESS 1
VALID
VALID
ADDRESS 6
td(E)S (27)
(28)
(25)
th(A)SR
(31)
(30)
tsu(A)SR (29)
tdis(E)SR (26)
th(A)SR (31)
tsu(A)SR
(29)
td(E)R
td(E)R
t:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the UL631H256 performs a
STORE or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
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