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April 7, 2005
UL631H256
L- to H-level
undefined
H- to L-level
i:
If W is low and when E goes low, the outputs remain in the high impedance state.
j:
E or W must be > VIH during address transitions.
Write Cycle #1: W-controlledj
Write Cycle #2: E-controlledj
th(D)
tcW
tsu(E)
th(A)
tw(W)
tsu(D)
tdis(W)
ten(W)
Address Valid
Input Data Valid
High Impedance
tsu(A-WH)
(12)
(16)
(13)
(19)
(20)
(23)
(21)
Previous Data
tsu(A)
Ai
E
W
DQi
Input
DQi
Output
tsu(A)
th(D)
tcW
tw(E)
th(A)
tsu(D)
Input Data Valid
tsu(W)
(12)
(18)
(21)
(20)
(19)
High Impedance
Address Valid
Ai
E
W
DQi
Input
DQi
Output
(17)
(15)
(12)
(15)
(14)