TE

CH

tm

T436416C

TM Technology Inc. reserves the right

P.10

Publication Date: AUG. 2004

to change products or specifications without notice.

Revision: A

MODE REGISTER

Register Programmed with MRS

Address

A13~A12

A11~A10/AP

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function

RFU

RFU

RF

U

TM

CAS Latency

BT

Burst Length

Test Mode

CAS Latency

Burst Type

Burst Length

A8

A7

Type

A6

A5

A4

Latency

A3

Type

A2

A1

A0

BT=0

BT=1

0

0

Mode Register Set

0

0

0

Reserved

0

Sequential

0

0

0

1

1

0

1

Reserved

0

0

1

Reserved

1

Interleave

0

0

1

2

2

1

0

Reserved

0

1

0

2

0

1

0

4

4

1

1

Reserved

0

1

1

3

0

1

1

8

8

1

0

0

Reserved

1

0

0

Reserved

Reserved

1

0

1

Reserved

1

0

1

Reserved

Reserved

1

1

0

Reserved

1

1

0

Reserved

Reserved

1

1

1

Reserved

1

1

1

Full Page

Reserved

Full Page Length : 256

Note : 1. RFU (reserved for future use) should stay “0” during MRS cycle.

2. Test mode use A7~A8, vendor specific options use A9, A10~A11 and A12~A13.

A7~A8, A10 /AP~A11 and A12~A13 must be set to low for normal SDRAM operation.

Refer to the table for specific codes for various burst length, burst type and CAS latencies.

Mode Register Write Timing

CL O C K

CK E

CS

RA S

CA S

WE

A0 - A 1 3