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IS42S16128 Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS42S16128 Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
7 / 75 page IS42S16128 ISSI® Integrated Silicon Solution, Inc. — 1-800-379-4774 7 Rev. A 03/13/00 OPERATING FREQUENCY / LATENCY RELATIONSHIPS -8 -10 -12 Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units — Clock Cycle Time 8 10 25 10 15 30 12 17 34 ns — Operating Frequency 125 100 40 100 65 33 83 58 29 MHz tCAC CAS Latency 3 2 1 3 2 1 3 2 1 cycle tRCD Active Command To Read/Write Command Delay Time 3 2 1 3 2 1 3 2 1 cycle tRAC RAS Latency (tRCD + tCAC) 6 4 2 6 4 2 6 4 2 cycle tRC Command Period (REF to REF / ACT to ACT) 9 5 2 9 6 3 9 7 4 cycle tRAS Command Period (ACT to PRE) 6 3 1 6 4 2 6 5 3 cycle tRP Command Period (PRE to ACT) 3 2 1 3 2 1 3 2 1 cycle tRRD Command Period (ACT[0] to ACT [1]) 3 2 1 3 2 1 3 2 1 cycle tCCD Column Command Delay Time 1 1 1 1 1 1 1 1 1 cycle (READ, READA, WRIT, WRITA) tDPL Input Data To Precharge Command Delay Time 1 1 1 1 1 1 1 1 1 cycle tDAL Input Data To Active/Refresh Command Delay Time 4 3 2 4 3 2 4 3 2 cycle (DuringAuto-Precharge) tRBD Burst Stop Command To Output in HIGH-Z Delay Time 3 2 1 3 2 1 3 2 1 cycle (Read) tWBD Burst Stop Command To Input in Invalid Delay Time 0 0 0 0 0 0 0 0 0 cycle (Write) tRQL Precharge Command To Output in HIGH-Z Delay Time 3 2 1 3 2 1 3 2 1 cycle (Read) tWDL Precharge Command To Input in Invalid Delay Time 0 0 0 0 0 0 0 0 0 cycle (Write) tPQL Last Output To Auto-Precharge Start Time (Read) –2 –10 –2 –10 –2 –1 0 cycle tQMD DQM To Output Delay Time (Read) 2 2 2 2 2 2 2 2 2 cycle tDMD DQM To Input Delay Time (Write) 0 0 0 0 0 0 0 0 0 cycle tMCD Mode Register Set To Command Delay Time 2 2 2 2 2 2 2 2 2 cycle AC TEST CONDITIONS (Input/Output Reference Level: 1.4V) Input Output Load 2.0V 1.4V 0.8V CLK INPUT OUTPUT tCHI tCH tAC tOH tCS tCK tCL 2.0V 1.4V 1.4V 1.4V 0.8V I/O 500 Ω +1.4V 50 pF |
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