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NCP1232 Datasheet(PDF) 2 Page - ON Semiconductor |
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NCP1232 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page NCP1232 http://onsemi.com 2 FUNCTIONAL BLOCK DIAGRAM VDCC 5%/10% TOLERANCE SELECT DEBOUNCE WATCHDOG TIMEBASE SELECT WATCHDOG TIMER RESET GENERATOR TOL PB RST TD RST RST ST GND NCP1232 REF PIN DESCRIPTION Pin No. (8–Pin SOIC) Symbol Description 1 PB RST Push–button Reset Input. A debounced active–low input that ignores pulses less than 1 msec in duration and is guaranteed to recognize inputs of 20 msec or greater. 2 TD Time Delay Set. The watchdog time–out select input (tTD = 150 msec for TD = 0 V, tTD = 600 msec for TD = open, tTD = 1.2 sec for TD = VCC.) 3 TOL Tolerance Input. Connect to GND for 5% tolerance or to VCC for 10% tolerance. 4 GND Ground. 5 RST Reset Output (Active High) – goes active: 1. If VCC falls below the selected reset voltage threshold 2. If PB RST is forced low 3. If ST is not strobed within the minimum time–out period 4. During power–up 6 RST Reset Output (Active Low, Open Drain) – see RST. 7 ST Strobe Input. Input for watchdog timer. 8 VCC The +5 V Power Supply Input. |
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