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HD6432341FA Datasheet(PDF) 10 Page - Hitachi Semiconductor |
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HD6432341FA Datasheet(HTML) 10 Page - Hitachi Semiconductor |
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10 / 907 page  iv 6.1.3 Pin Configuration ................................................................................................. 133 6.1.4 Register Configuration ......................................................................................... 133 6.2 Register Descriptions......................................................................................................... 134 6.2.1 Bus Width Control Register (ABWCR) ............................................................... 134 6.2.2 Access State Control Register (ASTCR).............................................................. 135 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 136 6.2.4 Bus Control Register H (BCRH).......................................................................... 139 6.2.5 Bus Control Register L (BCRL)........................................................................... 141 6.3 Overview of Bus Control................................................................................................... 142 6.3.1 Area Partitioning .................................................................................................. 142 6.3.2 Bus Specifications ................................................................................................ 144 6.3.3 Memory Interfaces................................................................................................ 145 6.3.4 Advanced Mode.................................................................................................... 145 6.3.5 Areas in Normal Mode (ZTAT, Mask ROM, and No On-Chip ROM Versions Only)...................................................................................................... 146 6.3.6 Chip Select Signals............................................................................................... 147 6.4 Basic Bus Interface............................................................................................................ 148 6.4.1 Overview .............................................................................................................. 148 6.4.2 Data Size and Data Alignment ............................................................................. 148 6.4.3 Valid Strobes ........................................................................................................ 150 6.4.4 Basic Timing ........................................................................................................ 151 6.4.5 Wait Control ......................................................................................................... 159 6.5 Burst ROM Interface ......................................................................................................... 161 6.5.1 Overview .............................................................................................................. 161 6.5.2 Basic Timing ........................................................................................................ 161 6.5.3 Wait Control ......................................................................................................... 163 6.6 Idle Cycle........................................................................................................................... 164 6.6.1 Operation .............................................................................................................. 164 6.6.2 Pin States in Idle Cycle ........................................................................................ 167 6.7 Bus Release........................................................................................................................ 167 6.7.1 Overview .............................................................................................................. 167 6.7.2 Operation .............................................................................................................. 167 6.7.3 Pin States in External Bus Released State............................................................ 168 6.7.4 Transition Timing ................................................................................................. 169 6.7.5 Usage Note ........................................................................................................... 170 6.8 Bus Arbitration .................................................................................................................. 170 6.8.1 Overview .............................................................................................................. 170 6.8.2 Operation .............................................................................................................. 170 6.8.3 Bus Transfer Timing ............................................................................................ 171 6.8.4 External Bus Release Usage Note ........................................................................ 171 6.9 Resets and the Bus Controller............................................................................................ 171 |
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