© Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1

Publication Order Number:

SN74LS109A/D

SN74LS109A

Dual JK Positive

Edge-Triggered Flip-Flop

The SN74LS109A consists of two high speed completely

independent transition clocked JK flip-flops. The clocking operation

is independent of rise and fall times of the clock waveform. The JK

design allows operation as a D flip-flop by simply connecting the J and

K pins together.

MODE SELECT – TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

J

K

Q

Q

Set

Reset (Clear)

*Undetermined

Load “1” (Set)

Hold

Toggle

Load “0” (Reset)

L

H

L

H

H

H

H

H

L

L

H

H

H

H

X

X

X

h

l

h

l

X

X

X

h

h

l

l

H

L

H

H

q

q

L

L

H

H

L

q

q

H

*

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

Supply Voltage

4.75

5.0

5.25

V

Operating Ambient

Temperature Range

0

25

70

°C

Output Current – High

– 0.4

mA

Output Current – Low

8.0

mA

LOW

POWER

SCHOTTKY

Device

Package

Shipping

ORDERING INFORMATION

SN74LS109AN

16 Pin DIP

2000 Units/Box

SN74LS109AD

16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC

N SUFFIX

CASE 648

16

1

16

1