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PE310G4DBIR Datasheet(HTML) 10 Page - Silicom Ltd. |
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PE310G4DBIR Datasheet(HTML) 10 Page - Silicom Ltd. |
![]() Silicom Ltd. Connectivity Solutions Page 10 Session balancing with L3/L4 hashing or other mechanism ISL (Inter Switch Link) Tagging per port can be added to the packets per configuration ISL Tagging can be removed and can be forward to specific port per the ISL index Quality of Service support with the following features: Priority levels: 16 internal “switch” priorities, 8 or 16 VLAN priorities (optional use of CFI bit as an extra VLAN priority bit) Arbitrary mapping of ingress VLAN priority to an internal VLAN priority Arbitrary mapping of an internal VLAN priority to egress VLAN priority Arbitrary mapping of internal VLAN priority to switch priority Arbitrary mapping of DSCP to switch priority, configurable priority source selection Scheduler: 8 traffic classes, arbitrary mapping of switch priorities to traffic class, deficit weighted round-robin or strict priority Notification: Two congestion notifications can be supported Virtual output queue congestion notification (VCN) and Intel proprietary backward congestion notification (FCN) Open Flow support (consistent with OpenFlow protocol standard) sFlow support User defined Packet transmission with two optional modes: 1. Simple mode – transmit on specific port. 2. Switched mode – where switch determines destination port/ports, or with specific information such as whether or not egress processing rules should be applied Storm Control Management – Switch can support a variety storm controller. Each storm controller can be programmable to define rat, condition (like unicast ICMP frames whose TTL is at most 1), frame type (can be OR’ed), ingress & egress port ports. Actions: do nothing, drops frames to port (according to filter) *Future SW supports Bypass / Disconnect Silicom’s Bypass adapter supports the following mode states: Normal/inline, Bypass/Fail-To-Wire and Disconnect modes. Normal/Inline mode In Normal mode, the ports are independent interfaces (see Figure 6: Normal mode, one Bypass pair is illustrated). |
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