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PE3100G2DQIR Datasheet(HTML) 2 Page - Silicom Ltd. |
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PE3100G2DQIR Datasheet(HTML) 2 Page - Silicom Ltd. |
![]() Silicom Ltd. Connectivity Solutions Page 2 Key Features Content Aware Director: Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other port (Bypass) Provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules that specify which packets are copied to the host system (TAP) Provides intelligent packet filtering / drop capability where rules specify which packets are directed to the host or dropped Provides redirection rules that can be defined using source IP/ destination IP / Source Port / Destination Port / VLAN tuples Redirection and packet filtering / drop are performed by the hardware itself in wire speed and do not require any software and CPU host system power processing Intelligent redirect mechanism is controllable via software Intelligent routing mechanism is controllable via software Support 2x100G / QSFP28 ports 100G QSFP28 Ports support 100GBase-SR4 and 100GBase-LR4 40G QSFP28 Ports support 40GBase-SR4 and 40GBase-LR4 Common Key features: Host Interface: PCI Express X16 lane Support PCI Express Base Specification Revision 3.0, 8GT/s, 5GT/s or 2.5GT/s Intel FM10420 Features: Single-element 4MB shared memory L2/L3/L4/OpenFlow forwarding & ACLs Stateless load balancing to CPUs Datacenter Bridging (lossless Ethernet) 32K 40-bit TCAM entries 16K MAC & NextHop tables Up to 300Gbps High-bandwidth CPU interface 2x 50Gbps 8-lane PCIe interfaces 4x 25Gbps 4-lane PCIe interfaces Up to 8 25G/10G/2.5G/1G ports Up to 2 40G (4 x 10G) usa.com - www.silicom |
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