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LTC3114-1 Datasheet(PDF) 26 Page - Analog Devices |
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LTC3114-1 Datasheet(HTML) 26 Page - Analog Devices |
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26 / 34 page  LTC3114-1 26 Rev. D For more information www.analog.com APPLICATIONS INFORMATION is simply a matter of substituting different values in the equations provided and reviewing the Bode plots, mak- ing minor adjustments as needed. Since the compen- sation design procedure uses a simplified model of the LTC3114-1, the results from the following compensation design should always be verified with time domain step load response tests to validate the effectiveness of the compensation design. It is assumed that the value and type of output capacitor will be selected based on the guidelines provided elsewhere in this data sheet. Particular attention needs to be paid to the voltage bias effect on ceramic capacitors typically used for output bypassing. Similarly, it is assumed that the inductor value and current rating has been selected as well based on the application requirements. Example Application Details: VIN = 9V to 36V VOUT = 12V Maximum IOUT (boost mode) = 700mA, RLOAD (min) = 12V/0.7A = 17.1Ω Maximum IOUT (buck mode) = 1A, RLOAD (min) = 12Ω COUT = 44µF L = 10µH Since this application includes boost mode operation, the first step is to calculate the worst-case RHPZ frequency as this will dictate the maximum loop bandwidth for the converter: RHPZ(f) = VIN2 •RLOAD VOUT2 • 2π •L (Hz) substituting the values mentioned earlier yields: RHPZ(f) = 9V2 • 17.1 Ω 12V2 • 2 π • 10µH = 153.1kHz In order to account for internal IC component variations, it is good practice to set the converter bandwidth or cross- over frequency at least three times lower than the RHPZ frequency to avoid excessive phase loss from the RHPZ when operating in boost mode. In some instances such as higher output voltage applications, an even greater separation between the loop crossover frequency and the RHPZ frequency may be necessary. In this example design, we’ll plan to achieve a loop bandwidth (fCC) of 29kHz or approximately one-fifth the RHPZ frequency. The system poles and zeros are as follows: Output Load Pole (P1) = 1 2 π •RLOAD •COUT ; buck mode, where RLOAD = output resistance. In boost mode this equation is slightly different: 2 2 π •RLOAD •COUT ( )′ , but with the reduced output current capability in boost (higher RLOAD), the load pole location is about the same. Error Amp Pole (P2) = 1 2 π •REA •CC ( ) ; this pole is very close to DC, REA = error amp output resistance, which is approximately 3.6MΩ. It has no impact on the compensation design, but is included here for completeness. Compensation Zero (Z1) = 1 2 π •RZ •CP1 ( ) ; RZ and CP1 are the error amp compensation compo- nents that will be selected. Ignoring very high frequency output capacitor ESR zero and secondary high frequency error amp pole, the system has two poles and one zero. The error amp pole (P2) is always near DC and we have little influence on it. The output load pole (P1) will move depending on buck-boost converter load resistance. The highest frequency for P1, the output load pole, is at maximum load current (min- imum RLOAD). If we design the error amp zero (Z1) fre- quency so that it coincides with P1(max), then we will get the maximum phase benefit from the compensation net- work at full load and enough phase boost at lighter loads for stable operation and a single pole response where the loop crosses zero dB. |
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