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ST7LITE3 Datasheet(PDF) 76 Page - STMicroelectronics |
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ST7LITE3 Datasheet(HTML) 76 Page - STMicroelectronics |
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76 / 167 page  ST7LITE3 76/167 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 Main Features ■ Full duplex synchronous transfers (on 3 lines) ■ Simplex synchronous transfers (on 2 lines) ■ Master or slave operation ■ Six master mode frequencies (fCPU/4 max.) ■ fCPU/2 max. slave mode frequency (see note) ■ SS Management by software or hardware ■ Programmable clock polarity and phase ■ End of transfer interrupt flag ■ Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 General Description Figure 47 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: – SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR) The SPI is connected to external devices through 4 pins: – MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in- put by SPI slaves – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven by stand- ard I/O ports on the master Device. 1 |
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