SPEAR-09-H022 datasheet(9/55 Pages) STMICROELECTRONICS

Part #	SPEAR-09-H022

Description	SPEAr Head ARM 926, 200K customizable eASIC gates, large IP portfolio SoC

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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SPEAR-09-H022

3 Features

9/55

3

Features

3.1

CPU

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ARM926EJ-S RISC Processor

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fMAX 266 MHz (downward scalable)

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Virtual address support with MMU

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32 KB instruction CACHE (4 way set associative)

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16 KB data CACHE (4 way set associative)

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8 KB instruction TCM

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8 KB data TCM

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Coprocessor interface

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JTAG

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ETM9 (rev 2.2), large size FIFO

3.2

INTERNAL BUS STRUCTURES

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Multilayer structure AMBA 2.0 compliant

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fMAX 133 MHz

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High speed I/Os with embedded DMA function

3.3

CLOCK SYSTEM

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Programmable clock generator

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PLL with E.M.I. reduction

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Low Jitter PLL for USB 2.0

3.4

INTERRUPT CONTROLLER

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IRQ and FIQ interrupt generations

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Support up to 32 standard interrupts

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Support up to 16 vectored interrupts

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Software interrupt generation

3.5

MEMORY SYSTEM

MEMORY ON CHIP

16 KBytes single-port SRAM connected to eASIC MacroCell.

It can be used on AHB Bus or directly by the custom logic.

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SPEAR-09-H022 Datasheet(PDF) 9 Page - STMicroelectronics

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