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TMS28F033-33BPAFQ Datasheet(PDF) 7 Page - Texas Instruments |
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TMS28F033-33BPAFQ Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 52 page  TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 overlay block (continued) Table 3. Methods of Setting/Clearing the Overlay-Block-Enable Bit (OBEB) METHOD PRIOR STATE OF OBEB NEXT STATE OF OBEB Toggle RP with VPP ≥ VPPH X† 1 Toggle RP with VPP ≤ VPPL X† 0 Power-on-reset of VDDI with VPP ≥ VPPH X† 1 Power-on-reset of VDDI with VPP ≤ VPPL X† 0 Issue CSM command 06h 0 1 Enable/disable overlay block for reads 1 0 † X is a don’t care. The enable/disable-overlay-block CSM command (06h) is used to enable the overlay block for a read operation, or to disable the overlay block after a read operation. When 06h is issued for overlay-block access, both the overlay-block latch and OBEB are set whether VPP ≥ VPPH or not. However, only the overlay block is enabled (and only OBS is set) if VPP ≥ VPPH. Software Enable VPP RP / SRESET Power-On Reset Software Disable Overlay Block Control VPP OBEB OBS CLR D SET Q Figure 3. Overlay-Block-Control Functional Diagram command state machine (CSM) Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface between the external microprocessor and the internal WSM. The available commands are listed in Table 4 and the corresponding descriptions are in Table 5. When a program or erase command is issued to the CSM, the WSM controls the internal sequences and the CSM responds only to status reads. A command is valid only if the exact sequence of writes is completed. After the WSM completes its task, the WSM status bit (SB7) is set to a logic-high level, allowing the CSM to respond to the full command set again. In addition, Ready/Busy (RY/BY) is an optional output that is available to monitor the WSM status. operation Device operations are selected by entering standard JEDEC 8-bit command codes with conventional microprocessor timing into an on-chip CSM through I/O pins DQ0 – DQ7. When the device is powered up, internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation requires a command code to be entered into the CSM. The on-chip status register allows the progress of various operations to be monitored. The status register is interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data on I/O pins DQ0 – DQ7 (cycle 2). Status register bits SB0 through SB7 correspond to DQ0 through DQ7. |
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