8

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36

IDT72V3683L10

IDT72V3683L15

IDT72V3693L10

IDT72V3693L15

IDT72V36103L10 IDT72V36103L15

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

—

100

—

66.7

MHz

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

Setup Time, A0-A35 before CLKA

↑ and B0-B35 before CLKB↑

3—

4

—

ns

Setup Time,

CSAand W/RAbefore CLKA

↑; CSBand W/RB before CLKB↑

4

—

4.5

—

ns

Setup Time, ENA, and MBA before CLKA

↑; ENB and MBB before CLKB↑

3

—

4.5

—

ns

Setup Time,

RS1or PRSLOW before CLKA

5—

5

—

ns

Setup Time, FS0, FS1 and FS2 before

RS1 HIGH

7.5

—

7.5

—

ns

Setup Time, BE/

FWFT before RS1 HIGH

7.5

—

7.5

—

ns

Setup Time, FS0/SD before CLKA

↑

3—

4

—

ns

Setup Time, FS1/

SENbeforeCLKA

↑

3—

4

—

ns

Setup Time, FWFT before CLKA

↑

0—

0

—

ns

Hold Time, A0-A35 after CLKA

↑ and B0-B35 after CLKB↑

0.5

—

1

—

ns

Setup Time, RTM before

RT1; RTM before RT2

5—

5

—

ns

Hold Time,

CSA, W/RA, ENA, and MBA after CLKA

↑; CSB, W/RB, ENB, and MBB

0.5

—

1

—

ns

afterCLKB

↑

Hold Time,

RS1 or PRS LOW after CLKA

4—

4

—

ns

Hold Time, FS0, FS1 and FS2 after

RS1 HIGH

2

—

2

—

ns

Hold Time, BE/

FWFT after RS1 HIGH

2

—

2

—

ns

Hold Time, FS0/SD after CLKA

↑

0.5

—

1

—

ns

Hold Time, FS1/

SENHIGH after CLKA

↑

0.5

—

1

—

ns

Hold Time, FS1/

SEN HIGH after RS1 HIGH

2

—

2

—

ns

Hold Time, RTM after

RT1; RTM after RT2

5—

5

—

ns

Skew Time between CLKA

↑ and CLKB↑ for EF/OR and FF/IR

5

—

7.5

—

ns

Skew Time between CLKA

↑ and CLKB↑ for AE and AF

12

—

12

—

ns

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

3. Design simulated, not tested.