GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)

Rev: 1.04 10/2004

32/39

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Timing Diagram

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

2.0

V1

3.3 V Test Port Input Low Voltage

–0.3

0.8

V

1

2.5 V Test Port Input High Voltage

V1

2.5 V Test Port Input Low Voltage

–0.3

V1

TMS, TCK and TDI Input Leakage Current

–300

1

uA

2

TMS, TCK and TDI Input Leakage Current

–1

100

uA

3

TDO Output Leakage Current

–11

uA

4

Test Port Output High Voltage

1.7

—

V5, 6

Test Port Output Low Voltage

—

0.4

V

5, 7

Test Port Output CMOS High

—

V5, 8

Test Port Output CMOS Low

—

100 mV

V

5, 9

Notes:

3. 0 V

tTH

tTS

tTKQ

tTH

tTS

tTH

tTS

tTKL

tTKL

tTKH

tTKH

tTKC

tTKC

TCK

TDI

TMS

TDO

Parallel SRAM input